From 07d6fcfb34d955ceeed1f92f6064aa88443e327b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?B=C3=A1n=20D=C3=A9nes?= Date: Sat, 3 Dec 2022 18:11:11 +0100 Subject: [PATCH] Improve PCB test readability --- test/index.js | 5 +- test/pcbs/mock_footprints___pcbs.json | 3 - .../mock_footprints___pcbs_main.kicad_pcb | 190 ++++++++++++++++++ test/pcbs/references___pcbs.json | 4 - test/pcbs/references___pcbs_hidden.kicad_pcb | 112 +++++++++++ test/pcbs/references___pcbs_shown.kicad_pcb | 112 +++++++++++ 6 files changed, 417 insertions(+), 9 deletions(-) delete mode 100644 test/pcbs/mock_footprints___pcbs.json create mode 100644 test/pcbs/mock_footprints___pcbs_main.kicad_pcb delete mode 100644 test/pcbs/references___pcbs.json create mode 100644 test/pcbs/references___pcbs_hidden.kicad_pcb create mode 100644 test/pcbs/references___pcbs_shown.kicad_pcb diff --git a/test/index.js b/test/index.js index 34d4f9c..e1fc995 100644 --- a/test/index.js +++ b/test/index.js @@ -55,8 +55,9 @@ const test = function(input_path) { } else { fs.writeJSONSync(expected_path, output_part, {spaces: 4}) } + } else { + output_part.should.deep.equal(expected) } - output_part.should.deep.equal(expected) } }) } @@ -79,7 +80,7 @@ if (what) { }) } } else { - for (const part of ['points', 'outlines', 'cases', 'pcbs']) { + for (const part of ['points', 'outlines', 'cases', 'pcbs', 'footprints']) { describe(cap(part), function() { for (const i of glob.sync(path.join(__dirname, part, '*.yaml'))) { test.call(this, i) diff --git a/test/pcbs/mock_footprints___pcbs.json b/test/pcbs/mock_footprints___pcbs.json deleted file mode 100644 index c4083c7..0000000 --- a/test/pcbs/mock_footprints___pcbs.json +++ /dev/null @@ -1,3 +0,0 @@ -{ - "main": "\n \n(kicad_pcb (version 20171130) (host pcbnew 5.1.6)\n\n (page A3)\n (title_block\n (title main)\n (rev v1.0.0)\n (company Unknown)\n )\n\n (general\n (thickness 1.6)\n )\n\n (layers\n (0 F.Cu signal)\n (31 B.Cu signal)\n (32 B.Adhes user)\n (33 F.Adhes user)\n (34 B.Paste user)\n (35 F.Paste user)\n (36 B.SilkS user)\n (37 F.SilkS user)\n (38 B.Mask user)\n (39 F.Mask user)\n (40 Dwgs.User user)\n (41 Cmts.User user)\n (42 Eco1.User user)\n (43 Eco2.User user)\n (44 Edge.Cuts user)\n (45 Margin user)\n (46 B.CrtYd user)\n (47 F.CrtYd user)\n (48 B.Fab user)\n (49 F.Fab user)\n )\n\n (setup\n (last_trace_width 0.25)\n (trace_clearance 0.2)\n (zone_clearance 0.508)\n (zone_45_only no)\n (trace_min 0.2)\n (via_size 0.8)\n (via_drill 0.4)\n (via_min_size 0.4)\n (via_min_drill 0.3)\n (uvia_size 0.3)\n (uvia_drill 0.1)\n (uvias_allowed no)\n (uvia_min_size 0.2)\n (uvia_min_drill 0.1)\n (edge_width 0.05)\n (segment_width 0.2)\n (pcb_text_width 0.3)\n (pcb_text_size 1.5 1.5)\n (mod_edge_width 0.12)\n (mod_text_size 1 1)\n (mod_text_width 0.15)\n (pad_size 1.524 1.524)\n (pad_drill 0.762)\n (pad_to_mask_clearance 0.05)\n (aux_axis_origin 0 0)\n (visible_elements FFFFFF7F)\n (pcbplotparams\n (layerselection 0x010fc_ffffffff)\n (usegerberextensions false)\n (usegerberattributes true)\n (usegerberadvancedattributes true)\n (creategerberjobfile true)\n (excludeedgelayer true)\n (linewidth 0.100000)\n (plotframeref false)\n (viasonmask false)\n (mode 1)\n (useauxorigin false)\n (hpglpennumber 1)\n (hpglpenspeed 20)\n (hpglpendiameter 15.000000)\n (psnegative false)\n (psa4output false)\n (plotreference true)\n (plotvalue true)\n (plotinvisibletext false)\n (padsonsilk false)\n (subtractmaskfromsilk false)\n (outputformat 1)\n (mirror false)\n (drillshape 1)\n (scaleselection 1)\n (outputdirectory \"\"))\n )\n\n (net 0 \"\")\n(net 1 \"P1\")\n(net 2 \"T3_1\")\n(net 3 \"T3_2\")\n(net 4 \"T3_3\")\n \n (net_class Default \"This is the default net class.\"\n (clearance 0.2)\n (trace_width 0.25)\n (via_dia 0.8)\n (via_drill 0.4)\n (uvia_dia 0.3)\n (uvia_drill 0.1)\n (add_net \"\")\n(add_net \"P1\")\n(add_net \"T3_1\")\n(add_net \"T3_2\")\n(add_net \"T3_3\")\n )\n\n \n\n (module trace_test (layer F.Cu) (tedit 5CF31DEF)\n\n (at 1 -1 30)\n\n (pad 1 smd rect (at 0 0 30) (size 1 1) (layers F.Cu F.Paste F.Mask)\n (net 1 \"P1\") (solder_mask_margin 0.2))\n\n (pad 2 smd rect (at 5 5 30) (size 1 1) (layers F.Cu F.Paste F.Mask)\n (net 1 \"P1\") (solder_mask_margin 0.2))\n\n )\n\n (segment (start 1 -1) (end 7.830127 0.8301270000000001) (width 0.25) (layer F.Cu) (net 1))\n\n \n\n\n (module zone_test (layer F.Cu) (tedit 5CF31DEF)\n\n (at 1 -1 30)\n\n (pad 1 smd rect (at 0 0 30) (size 1 1) (layers F.Cu F.Paste F.Mask)\n (net 1 \"P1\") (solder_mask_margin 0.2))\n\n (pad 2 smd rect (at 5 5 30) (size 1 1) (layers F.Cu F.Paste F.Mask)\n (net 1 \"P1\") (solder_mask_margin 0.2))\n\n )\n\n (zone (net 1) (net_name P1) (layer F.Cu) (tstamp 0) (hatch full 0.508)\n (connect_pads (clearance 0.508))\n (min_thickness 0.254)\n (fill yes (arc_segments 32) (thermal_gap 0.508) (thermal_bridge_width 0.508))\n (polygon (pts (xy 7.830127 0.8301270000000001) (xy 2.830127 -7.830127) (xy -5.830127 -2.830127) (xy -0.8301270000000001 5.830127)))\n )\n\n \n \n\n (module dynamic_net_test (layer F.Cu) (tedit 5CF31DEF)\n\n (at 0 0 0)\n\n (pad 1 smd rect (at 0 0 0) (size 1 1) (layers F.Cu F.Paste F.Mask)\n (net 2 \"T3_1\") (solder_mask_margin 0.2))\n\n (pad 1 smd rect (at 0 0 0) (size 1 1) (layers F.Cu F.Paste F.Mask)\n (net 3 \"T3_2\") (solder_mask_margin 0.2))\n\n (pad 1 smd rect (at 0 0 0) (size 1 1) (layers F.Cu F.Paste F.Mask)\n (net 4 \"T3_3\") (solder_mask_margin 0.2))\n\n )\n\n \n \n\n (module anchor_test (layer F.Cu) (tedit 5CF31DEF)\n\n (at 0 0 0)\n\n (fp_line (start 0 0) (end 10 -10) (layer Dwgs.User) (width 0.05))\n\n )\n\n \n (gr_line (start -9.5 9.5) (end 9.5 9.5) (angle 90) (layer Edge.Cuts) (width 0.15))\n(gr_line (start 9.5 9.5) (end 9.5 -9.5) (angle 90) (layer Edge.Cuts) (width 0.15))\n(gr_line (start 9.5 -9.5) (end -9.5 -9.5) (angle 90) (layer Edge.Cuts) (width 0.15))\n(gr_line (start -9.5 -9.5) (end -9.5 9.5) (angle 90) (layer Edge.Cuts) (width 0.15))\n \n)\n\n " -} \ No newline at end of file diff --git a/test/pcbs/mock_footprints___pcbs_main.kicad_pcb b/test/pcbs/mock_footprints___pcbs_main.kicad_pcb new file mode 100644 index 0000000..f3a1b49 --- /dev/null +++ b/test/pcbs/mock_footprints___pcbs_main.kicad_pcb @@ -0,0 +1,190 @@ + + +(kicad_pcb (version 20171130) (host pcbnew 5.1.6) + + (page A3) + (title_block + (title main) + (rev v1.0.0) + (company Unknown) + ) + + (general + (thickness 1.6) + ) + + (layers + (0 F.Cu signal) + (31 B.Cu signal) + (32 B.Adhes user) + (33 F.Adhes user) + (34 B.Paste user) + (35 F.Paste user) + (36 B.SilkS user) + (37 F.SilkS user) + (38 B.Mask user) + (39 F.Mask user) + (40 Dwgs.User user) + (41 Cmts.User user) + (42 Eco1.User user) + (43 Eco2.User user) + (44 Edge.Cuts user) + (45 Margin user) + (46 B.CrtYd user) + (47 F.CrtYd user) + (48 B.Fab user) + (49 F.Fab user) + ) + + (setup + (last_trace_width 0.25) + (trace_clearance 0.2) + (zone_clearance 0.508) + (zone_45_only no) + (trace_min 0.2) + (via_size 0.8) + (via_drill 0.4) + (via_min_size 0.4) + (via_min_drill 0.3) + (uvia_size 0.3) + (uvia_drill 0.1) + (uvias_allowed no) + (uvia_min_size 0.2) + (uvia_min_drill 0.1) + (edge_width 0.05) + (segment_width 0.2) + (pcb_text_width 0.3) + (pcb_text_size 1.5 1.5) + (mod_edge_width 0.12) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 1.524 1.524) + (pad_drill 0.762) + (pad_to_mask_clearance 0.05) + (aux_axis_origin 0 0) + (visible_elements FFFFFF7F) + (pcbplotparams + (layerselection 0x010fc_ffffffff) + (usegerberextensions false) + (usegerberattributes true) + (usegerberadvancedattributes true) + (creategerberjobfile true) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "")) + ) + + (net 0 "") +(net 1 "P1") +(net 2 "T3_1") +(net 3 "T3_2") +(net 4 "T3_3") + + (net_class Default "This is the default net class." + (clearance 0.2) + (trace_width 0.25) + (via_dia 0.8) + (via_drill 0.4) + (uvia_dia 0.3) + (uvia_drill 0.1) + (add_net "") +(add_net "P1") +(add_net "T3_1") +(add_net "T3_2") +(add_net "T3_3") + ) + + + + (module trace_test (layer F.Cu) (tedit 5CF31DEF) + + (at 1 -1 30) + + (pad 1 smd rect (at 0 0 30) (size 1 1) (layers F.Cu F.Paste F.Mask) + (net 1 "P1") (solder_mask_margin 0.2)) + + (pad 2 smd rect (at 5 5 30) (size 1 1) (layers F.Cu F.Paste F.Mask) + (net 1 "P1") (solder_mask_margin 0.2)) + + ) + + (segment (start 1 -1) (end 7.830127 0.8301270000000001) (width 0.25) (layer F.Cu) (net 1)) + + + + + (module zone_test (layer F.Cu) (tedit 5CF31DEF) + + (at 1 -1 30) + + (pad 1 smd rect (at 0 0 30) (size 1 1) (layers F.Cu F.Paste F.Mask) + (net 1 "P1") (solder_mask_margin 0.2)) + + (pad 2 smd rect (at 5 5 30) (size 1 1) (layers F.Cu F.Paste F.Mask) + (net 1 "P1") (solder_mask_margin 0.2)) + + ) + + (zone (net 1) (net_name P1) (layer F.Cu) (tstamp 0) (hatch full 0.508) + (connect_pads (clearance 0.508)) + (min_thickness 0.254) + (fill yes (arc_segments 32) (thermal_gap 0.508) (thermal_bridge_width 0.508)) + (polygon (pts (xy 7.830127 0.8301270000000001) (xy 2.830127 -7.830127) (xy -5.830127 -2.830127) (xy -0.8301270000000001 5.830127))) + ) + + + + + (module dynamic_net_test (layer F.Cu) (tedit 5CF31DEF) + + (at 0 0 0) + + (pad 1 smd rect (at 0 0 0) (size 1 1) (layers F.Cu F.Paste F.Mask) + (net 2 "T3_1") (solder_mask_margin 0.2)) + + (pad 1 smd rect (at 0 0 0) (size 1 1) (layers F.Cu F.Paste F.Mask) + (net 3 "T3_2") (solder_mask_margin 0.2)) + + (pad 1 smd rect (at 0 0 0) (size 1 1) (layers F.Cu F.Paste F.Mask) + (net 4 "T3_3") (solder_mask_margin 0.2)) + + ) + + + + + (module anchor_test (layer F.Cu) (tedit 5CF31DEF) + + (at 0 0 0) + + (fp_line (start 0 0) (end 10 -10) (layer Dwgs.User) (width 0.05)) + + ) + + + (gr_line (start -9.5 9.5) (end 9.5 9.5) (angle 90) (layer Edge.Cuts) (width 0.15)) +(gr_line (start 9.5 9.5) (end 9.5 -9.5) (angle 90) (layer Edge.Cuts) (width 0.15)) +(gr_line (start 9.5 -9.5) (end -9.5 -9.5) (angle 90) (layer Edge.Cuts) (width 0.15)) +(gr_line (start -9.5 -9.5) (end -9.5 9.5) (angle 90) (layer Edge.Cuts) (width 0.15)) + +) + + \ No newline at end of file diff --git a/test/pcbs/references___pcbs.json b/test/pcbs/references___pcbs.json deleted file mode 100644 index 0a24f58..0000000 --- a/test/pcbs/references___pcbs.json +++ /dev/null @@ -1,4 +0,0 @@ -{ - "shown": "\n \n(kicad_pcb (version 20171130) (host pcbnew 5.1.6)\n\n (page A3)\n (title_block\n (title shown)\n (rev v1.0.0)\n (company Unknown)\n )\n\n (general\n (thickness 1.6)\n )\n\n (layers\n (0 F.Cu signal)\n (31 B.Cu signal)\n (32 B.Adhes user)\n (33 F.Adhes user)\n (34 B.Paste user)\n (35 F.Paste user)\n (36 B.SilkS user)\n (37 F.SilkS user)\n (38 B.Mask user)\n (39 F.Mask user)\n (40 Dwgs.User user)\n (41 Cmts.User user)\n (42 Eco1.User user)\n (43 Eco2.User user)\n (44 Edge.Cuts user)\n (45 Margin user)\n (46 B.CrtYd user)\n (47 F.CrtYd user)\n (48 B.Fab user)\n (49 F.Fab user)\n )\n\n (setup\n (last_trace_width 0.25)\n (trace_clearance 0.2)\n (zone_clearance 0.508)\n (zone_45_only no)\n (trace_min 0.2)\n (via_size 0.8)\n (via_drill 0.4)\n (via_min_size 0.4)\n (via_min_drill 0.3)\n (uvia_size 0.3)\n (uvia_drill 0.1)\n (uvias_allowed no)\n (uvia_min_size 0.2)\n (uvia_min_drill 0.1)\n (edge_width 0.05)\n (segment_width 0.2)\n (pcb_text_width 0.3)\n (pcb_text_size 1.5 1.5)\n (mod_edge_width 0.12)\n (mod_text_size 1 1)\n (mod_text_width 0.15)\n (pad_size 1.524 1.524)\n (pad_drill 0.762)\n (pad_to_mask_clearance 0.05)\n (aux_axis_origin 0 0)\n (visible_elements FFFFFF7F)\n (pcbplotparams\n (layerselection 0x010fc_ffffffff)\n (usegerberextensions false)\n (usegerberattributes true)\n (usegerberadvancedattributes true)\n (creategerberjobfile true)\n (excludeedgelayer true)\n (linewidth 0.100000)\n (plotframeref false)\n (viasonmask false)\n (mode 1)\n (useauxorigin false)\n (hpglpennumber 1)\n (hpglpenspeed 20)\n (hpglpendiameter 15.000000)\n (psnegative false)\n (psa4output false)\n (plotreference true)\n (plotvalue true)\n (plotinvisibletext false)\n (padsonsilk false)\n (subtractmaskfromsilk false)\n (outputformat 1)\n (mirror false)\n (drillshape 1)\n (scaleselection 1)\n (outputdirectory \"\"))\n )\n\n (net 0 \"\")\n \n (net_class Default \"This is the default net class.\"\n (clearance 0.2)\n (trace_width 0.25)\n (via_dia 0.8)\n (via_drill 0.4)\n (uvia_dia 0.3)\n (uvia_drill 0.1)\n (add_net \"\")\n )\n\n references shown\n \n \n)\n\n ", - "hidden": "\n \n(kicad_pcb (version 20171130) (host pcbnew 5.1.6)\n\n (page A3)\n (title_block\n (title hidden)\n (rev v1.0.0)\n (company Unknown)\n )\n\n (general\n (thickness 1.6)\n )\n\n (layers\n (0 F.Cu signal)\n (31 B.Cu signal)\n (32 B.Adhes user)\n (33 F.Adhes user)\n (34 B.Paste user)\n (35 F.Paste user)\n (36 B.SilkS user)\n (37 F.SilkS user)\n (38 B.Mask user)\n (39 F.Mask user)\n (40 Dwgs.User user)\n (41 Cmts.User user)\n (42 Eco1.User user)\n (43 Eco2.User user)\n (44 Edge.Cuts user)\n (45 Margin user)\n (46 B.CrtYd user)\n (47 F.CrtYd user)\n (48 B.Fab user)\n (49 F.Fab user)\n )\n\n (setup\n (last_trace_width 0.25)\n (trace_clearance 0.2)\n (zone_clearance 0.508)\n (zone_45_only no)\n (trace_min 0.2)\n (via_size 0.8)\n (via_drill 0.4)\n (via_min_size 0.4)\n (via_min_drill 0.3)\n (uvia_size 0.3)\n (uvia_drill 0.1)\n (uvias_allowed no)\n (uvia_min_size 0.2)\n (uvia_min_drill 0.1)\n (edge_width 0.05)\n (segment_width 0.2)\n (pcb_text_width 0.3)\n (pcb_text_size 1.5 1.5)\n (mod_edge_width 0.12)\n (mod_text_size 1 1)\n (mod_text_width 0.15)\n (pad_size 1.524 1.524)\n (pad_drill 0.762)\n (pad_to_mask_clearance 0.05)\n (aux_axis_origin 0 0)\n (visible_elements FFFFFF7F)\n (pcbplotparams\n (layerselection 0x010fc_ffffffff)\n (usegerberextensions false)\n (usegerberattributes true)\n (usegerberadvancedattributes true)\n (creategerberjobfile true)\n (excludeedgelayer true)\n (linewidth 0.100000)\n (plotframeref false)\n (viasonmask false)\n (mode 1)\n (useauxorigin false)\n (hpglpennumber 1)\n (hpglpenspeed 20)\n (hpglpendiameter 15.000000)\n (psnegative false)\n (psa4output false)\n (plotreference true)\n (plotvalue true)\n (plotinvisibletext false)\n (padsonsilk false)\n (subtractmaskfromsilk false)\n (outputformat 1)\n (mirror false)\n (drillshape 1)\n (scaleselection 1)\n (outputdirectory \"\"))\n )\n\n (net 0 \"\")\n \n (net_class Default \"This is the default net class.\"\n (clearance 0.2)\n (trace_width 0.25)\n (via_dia 0.8)\n (via_drill 0.4)\n (uvia_dia 0.3)\n (uvia_drill 0.1)\n (add_net \"\")\n )\n\n references hidden\n \n \n)\n\n " -} diff --git a/test/pcbs/references___pcbs_hidden.kicad_pcb b/test/pcbs/references___pcbs_hidden.kicad_pcb new file mode 100644 index 0000000..9938111 --- /dev/null +++ b/test/pcbs/references___pcbs_hidden.kicad_pcb @@ -0,0 +1,112 @@ + + +(kicad_pcb (version 20171130) (host pcbnew 5.1.6) + + (page A3) + (title_block + (title hidden) + (rev v1.0.0) + (company Unknown) + ) + + (general + (thickness 1.6) + ) + + (layers + (0 F.Cu signal) + (31 B.Cu signal) + (32 B.Adhes user) + (33 F.Adhes user) + (34 B.Paste user) + (35 F.Paste user) + (36 B.SilkS user) + (37 F.SilkS user) + (38 B.Mask user) + (39 F.Mask user) + (40 Dwgs.User user) + (41 Cmts.User user) + (42 Eco1.User user) + (43 Eco2.User user) + (44 Edge.Cuts user) + (45 Margin user) + (46 B.CrtYd user) + (47 F.CrtYd user) + (48 B.Fab user) + (49 F.Fab user) + ) + + (setup + (last_trace_width 0.25) + (trace_clearance 0.2) + (zone_clearance 0.508) + (zone_45_only no) + (trace_min 0.2) + (via_size 0.8) + (via_drill 0.4) + (via_min_size 0.4) + (via_min_drill 0.3) + (uvia_size 0.3) + (uvia_drill 0.1) + (uvias_allowed no) + (uvia_min_size 0.2) + (uvia_min_drill 0.1) + (edge_width 0.05) + (segment_width 0.2) + (pcb_text_width 0.3) + (pcb_text_size 1.5 1.5) + (mod_edge_width 0.12) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 1.524 1.524) + (pad_drill 0.762) + (pad_to_mask_clearance 0.05) + (aux_axis_origin 0 0) + (visible_elements FFFFFF7F) + (pcbplotparams + (layerselection 0x010fc_ffffffff) + (usegerberextensions false) + (usegerberattributes true) + (usegerberadvancedattributes true) + (creategerberjobfile true) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "")) + ) + + (net 0 "") + + (net_class Default "This is the default net class." + (clearance 0.2) + (trace_width 0.25) + (via_dia 0.8) + (via_drill 0.4) + (uvia_dia 0.3) + (uvia_drill 0.1) + (add_net "") + ) + + references hidden + + +) + + \ No newline at end of file diff --git a/test/pcbs/references___pcbs_shown.kicad_pcb b/test/pcbs/references___pcbs_shown.kicad_pcb new file mode 100644 index 0000000..c5f0994 --- /dev/null +++ b/test/pcbs/references___pcbs_shown.kicad_pcb @@ -0,0 +1,112 @@ + + +(kicad_pcb (version 20171130) (host pcbnew 5.1.6) + + (page A3) + (title_block + (title shown) + (rev v1.0.0) + (company Unknown) + ) + + (general + (thickness 1.6) + ) + + (layers + (0 F.Cu signal) + (31 B.Cu signal) + (32 B.Adhes user) + (33 F.Adhes user) + (34 B.Paste user) + (35 F.Paste user) + (36 B.SilkS user) + (37 F.SilkS user) + (38 B.Mask user) + (39 F.Mask user) + (40 Dwgs.User user) + (41 Cmts.User user) + (42 Eco1.User user) + (43 Eco2.User user) + (44 Edge.Cuts user) + (45 Margin user) + (46 B.CrtYd user) + (47 F.CrtYd user) + (48 B.Fab user) + (49 F.Fab user) + ) + + (setup + (last_trace_width 0.25) + (trace_clearance 0.2) + (zone_clearance 0.508) + (zone_45_only no) + (trace_min 0.2) + (via_size 0.8) + (via_drill 0.4) + (via_min_size 0.4) + (via_min_drill 0.3) + (uvia_size 0.3) + (uvia_drill 0.1) + (uvias_allowed no) + (uvia_min_size 0.2) + (uvia_min_drill 0.1) + (edge_width 0.05) + (segment_width 0.2) + (pcb_text_width 0.3) + (pcb_text_size 1.5 1.5) + (mod_edge_width 0.12) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 1.524 1.524) + (pad_drill 0.762) + (pad_to_mask_clearance 0.05) + (aux_axis_origin 0 0) + (visible_elements FFFFFF7F) + (pcbplotparams + (layerselection 0x010fc_ffffffff) + (usegerberextensions false) + (usegerberattributes true) + (usegerberadvancedattributes true) + (creategerberjobfile true) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "")) + ) + + (net 0 "") + + (net_class Default "This is the default net class." + (clearance 0.2) + (trace_width 0.25) + (via_dia 0.8) + (via_drill 0.4) + (uvia_dia 0.3) + (uvia_drill 0.1) + (add_net "") + ) + + references shown + + +) + + \ No newline at end of file