2018-10-22 12:37:03 -07:00
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/*
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Copyright 2012 Jun Wako <wakojun@gmail.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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2019-11-13 00:38:37 -08:00
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2021-03-17 17:48:09 -07:00
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/* key matrix size */
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2018-10-22 12:37:03 -07:00
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#define MATRIX_ROWS 16 // keycode bit: 3-0
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#define MATRIX_COLS 8 // keycode bit: 6-4
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/* key combination for command */
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#define IS_COMMAND() ( \
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2022-10-16 06:14:40 -07:00
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get_mods() == (MOD_BIT(KC_LSFT) | MOD_BIT(KC_RSFT)) || \
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get_mods() == (MOD_BIT(KC_LCTL) | MOD_BIT(KC_RSFT)) \
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2018-10-22 12:37:03 -07:00
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)
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2021-03-17 17:48:09 -07:00
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#define XT_CLOCK_PIN D1
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#define XT_DATA_PIN D0
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#define XT_RST_PIN B7
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2018-10-22 12:37:03 -07:00
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/* hard reset: low pulse for 500ms and after that HiZ for safety */
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#define XT_RESET() do { \
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2021-03-17 17:48:09 -07:00
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writePinLow(XT_RST_PIN); \
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setPinOutput(XT_RST_PIN); \
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wait_ms(500); \
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setPinInput(XT_RST_PIN); \
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2018-10-22 12:37:03 -07:00
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} while (0)
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/* INT1 for falling edge of clock line */
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2021-03-17 17:48:09 -07:00
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#define XT_INT_INIT() do { \
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EICRA |= ((1 << ISC11) | (0 << ISC10)); \
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2018-10-22 12:37:03 -07:00
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} while (0)
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2021-03-17 17:48:09 -07:00
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2018-10-22 12:37:03 -07:00
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/* clears flag and enables interrupt */
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2021-03-17 17:48:09 -07:00
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#define XT_INT_ON() do { \
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EIFR |= (1 << INTF1); \
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EIMSK |= (1 << INT1); \
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2018-10-22 12:37:03 -07:00
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} while (0)
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2021-03-17 17:48:09 -07:00
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#define XT_INT_OFF() do { \
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EIMSK &= ~(1 << INT1); \
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2018-10-22 12:37:03 -07:00
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} while (0)
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2021-03-17 17:48:09 -07:00
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#define XT_INT_VECT INT1_vect
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