Commit Graph

4 Commits

Author SHA1 Message Date
James Young
7d1194de01
run: qmk cformat --core-only 2021-05-29 13:53:10 -07:00
Sergey Vlasov
65c9752762
Update ADC driver for STM32F1xx, STM32F3xx, STM32F4xx (#12403)
* Fix default ADC_RESOLUTION for ADCv3 (and ADCv4)

Recent ChibiOS update removed ADC_CFGR1_RES_10BIT from the ADCv3 headers
(that macro should not have been there, because ADCv3 has CFGR instead of
CFGR1).  Fix the default value for ADC_RESOLUTION to use ADC_CFGR_RES_10BITS
if it is defined (that name is used for ADCv3 and ADCv4).

* Update ADC docs to match the actually used resolution

ADC driver for ChibiOS actually uses the 10-bit resolution by default
(probably to match AVR); fix the documentation accordingly.  Also add
both ADC_CFGR_RES_10BITS and ADC_CFGR1_RES_10BIT constants (these names
differ according to the ADC implementation in the particular MCU).

* Fix pinToMux() for B12 and B13 on STM32F3xx

Testing on STM32F303CCT6 revealed that the ADC mux values for B12 and
B13 pins were wrong.

* Add support for all possible analog pins on STM32F1xx

Added ADC mux values for pins A0...A7, B0, B1, C0...C5 on STM32F1xx
(they are the same at least for STM32F103x8 and larger F103 devices, and
also F102, F105, F107 families).  Actually tested on STM32F103C8T6
(therefore pins C0...C5 were not tested).

Pins F6...F10, which are present on STM32F103x[C-G] in 144-pin packages,
cannot be supported at the moment, because those pins are connected only
to ADC3, but the ChibiOS ADC driver for STM32F1xx supports only ADC1.

* Add support for all possible analog pins on STM32F4xx

Added ADC mux values for pins A0...A7, B0, B1, C0...C5 and optionally
F3...F10 (if STM32_ADC_USE_ADC3 is enabled).  These mux values are
apparently the same for all F4xx devices, except some smaller devices may
not have ADC3.

Actually tested on STM32F401CCU6, STM32F401CEU6, STM32F411CEU6 (using
various WeAct “Blackpill” boards); only pins A0...A7, B0, B1 were tested.

Pins F3...F10 are inside `#if STM32_ADC_USE_ADC3` because some devices
which don't have ADC3 also don't have the GPIOF port, therefore the code
which refers to Fx pins does not compile.

* Fix STM32F3xx ADC mux table in documentation

The ADC driver documentation had some errors in the mux table for STM32F3xx.
Fix this table to match the datasheet and the actual code (mux settings for
B12 and B13 were also tested on a real STM32F303CCT6 chip).

* Add STM32F1xx ADC pins to the documentation

* Add STM32F4xx ADC pins to the documentation
2021-04-25 11:15:37 +10:00
Ryan
501f2fdef1
Normalise include statements in core code (#11153)
* Normalise include statements in core code

* Missed one
2020-12-11 13:45:24 +11:00
Joel Challis
d96380e654
Initial arm->chibios pass - simplify some platform logic (#8450) 2020-03-21 16:20:04 +11:00